In modern CMOS technology, there is a trend towards using fully silicided (FUSI) gates. In such devices it is desirable to have a specific gate silicide on N-channel MOS transistors, and a different gate silicide on P-channel MOS transistors. The suicides can be suicides of different metals or suicides of the same metal with different stoichiometric characteristics. Such different stoichiometric characteristics result, for example, from the reaction of silicon layers with metal layers of different thicknesses. Generally, forming gates of different types requires a dedicated masking step in order to separate the formation of the silicide for the gate electrodes of the NMOS devices from that of the silicide of the gate electrodes of the PMOS devices.
FIGS. 1A to 1E illustrate schematically a known method of forming a semiconductor device having gates, the upper parts of which comprise different suicide types, as described in U.S. application 2005/0156208 (this document does not disclose FUSI gates). In these figures, the left side corresponds to a P-channel MOS 100 and the right side corresponds to an N-channel MOS 102, both partway through fabrication. PMOS 100 includes a polycrystalline silicon gate 104, spacers 106, 108 and a gate dielectric 110. NMOS 102 includes a polycrystalline silicon gate 114, spacers 116, 118 and a gate dielectric 120. Source/drain regions 122, 124 are formed on both sides of the PMOS gate structure and source/drain regions 126, 128 are formed on both sides of the NMOS gate structure.
As shown in FIG. 1A, the PMOS transistor 100 is covered with a hard mask 130, for example a silicon oxide layer, which results from a deposition of a SiO2 layer in a photolithographic step.
FIG. 1B shows a next step in which first metal layers 142, 144, are deposited over PMOS 100 and NMOS 102 respectively, the metal layers comprising the same metal. An annealing step is then implemented such that metal silicide areas 146, 148 are formed in source/drain regions 126, 128 respectively and metal silicide is formed in area 150 of gate 114 of NMOS 102, but not in those parts of PMOS 100, which are protected by hard mask 130.
As shown in FIG. 1C, un-reacted metals are then removed from the PMOS 100 and NMOS 102, using a metal etch, and hard mask 130 is also removed from PMOS 100, using an etching process such as wet etching or dry etching.
Next, as shown in FIG. 1D, second metal layers 152, 154 are deposited over PMOS 100 and NMOS 102 respectively, the metal layers comprising a metal different to the first metal used for layers 142, 144. An annealing step is again implemented, resulting in metal silicide areas 156,158 being formed in the source/drain regions 122, 124 respectively and metal silicide is formed in area 160 of PMOS 100.
As shown in FIG. 1E, after un-reacted metals have been removed using a metal etch, PMOS transistor 100 has been formed with source/drain regions 156, 158 and region 160 of the gate being of a first metal silicide, and NMOS transistor 102 has been formed with source/drain regions 146, 148 and region 150 of the gate being of a second metal silicide.
The step for forming hard mask 130 described above in relation to FIG. 1A above requires a dedicated photolithography step, which is disadvantageous due to the extra time and cost associated with this process.
U.S. Pat. No. 6,204,103 (IBM) relates to CMOS circuits with different silicide gates for PMOS and NMOS transistors.
U.S. Patent Application 2005/0164433 relates to a method for making CMOS transistors.